FIG. 1 schematically illustrates a structural diagram of a memory cell in existing techniques. Referring to FIG. 1, the memory cell includes a substrate 10, a first control gate structure 102, a second control gate structure 112, a first floating gate structure 101, a second floating gate structure 111 and a word line structure 12 that are disposed on the substrate 10, and a first doped region 103 and a second doped region 113 disposed in the substrate 10.
The first floating gate structure 101 is disposed on the substrate 10 between the first doped region 103 and the word line structure 12, and the second floating gate structure 111 is disposed on the substrate 10 between the second doped region 113 and the word line structure 12. The first control gate structure 102 is disposed over the first floating gate structure 101, and the second control gate structure 112 is disposed over the second floating gate structure 111.
FIG. 2 schematically illustrates a circuit diagram of a memory which consists of a plurality of memory cells shown in FIG. 1. In the memory, one column of memory cell includes three memory cells, which is taken for example to describe a connection structure of the memory.
Memory cells in a same column are connected with two bit lines, where first doped regions of the memory cells in the same column are connected with a first bit line BL0, and the second doped regions of the memory cells in the same column are connected with a second bit line BL1. One end of the first bit line BL0 is connected with a pull-up cell 20, the other end of the first bit line BL0 is connected with a first end of a first isolation transistor ISO1, and a second end of the first isolation transistor ISO1 is connected with a column decoding cell 30. One end of the second bit line BL1 is connected with the pull-up cell 20, the other end of the second bit line BL1 is connected with a first end of a second isolation transistor ISO2, and a second end of the second isolation transistor ISO2 is connected with the column decoding cell 30.
Hereinafter, an erasing operation to the memory cells, and programming and reading operations of the first floating gate structure 101 are taken for examples to describe operation voltages in detail.
When the erasing operation is performed, a row decoding cell 40 applies voltage of 7V to 9V to the word line structure 12 which is connected with a word line WL0, applies voltage of −9V to −7V to the first control gate structure 102 which is connected with a first control line CG0, and applies voltage of −9V to −7V to the second control gate structure 112 which is connected with a second control line CG1. The pull-up cell 20 applies voltage of 0V to the first bit line BL0, and applies voltage of 0V to the second bit line BL1.
When the programming operation is performed, the row decoding cell 40 applies voltage of 1.3V to 1.6V to the word line structure 12 which is connected with the word line WL0, applies voltage of 7V to 9V to the first control gate structure 102 which is connected with the first control line CG0, and applies voltage of 4V to 6V to the second control gate structure 112 which is connected with the second control line CG1. The pull-up cell 20 applies programming current to the first bit line BL0, and applies voltage of 5V to 6V to the second bit line BL1.
When the reading operation is performed, the row decoding cell 40 applies voltage of 2V to 5V to the word line structure 12 which is connected with the word line WL0, applies voltage of 0V to the first control gate structure 102 which is connected with the first control line CG0, and applies voltage of 2.5V to 5V to the second control gate structure 112 which is connected with the second control line CG1. The pull-up cell 20 applies voltage of 0V to the first bit line BL0, and applies voltage of 0.4V to 0.8V to the second bit line BL1.
In the above memory, the first isolation transistor ISO1 and the second isolation transistor ISO2 having an isolation function are generally high voltage transistors, which may make the memory circuit have a relatively great size.